# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=mips64-mti-linux-gnu %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion | FileCheck %s --check-prefix=MIPS64
# RUN: llc -mtriple=mips64-mti-linux-gnu %s -o - -start-before mips-delay-slot-filler -stop-after mips-branch-expansion -relocation-model=pic | FileCheck %s --check-prefix=PIC

# Test the long branch expansion of various branches

--- |
  define i64 @expand_BEQ64(i64 %a, i64 %b) {
    %cmp = icmp eq i64 %a, %b
    br i1 %cmp, label %iftrue, label %tail

  iftrue:
    call void asm sideeffect ".space 131068", ""()
    ret i64 1

  tail:
    ret i64 0
  }

  define i64 @expand_BNE64(i64 %a, i64 %b) {
    %cmp = icmp eq i64 %a, %b
    br i1 %cmp, label %iftrue, label %tail

  iftrue:
    call void asm sideeffect ".space 131068", ""()
    ret i64 1

  tail:
    ret i64 0
  }

  define i64 @expand_BGEZ64(i64 %a, i64 %b) {
    %cmp = icmp eq i64 %a, %b
    br i1 %cmp, label %iftrue, label %tail

  iftrue:
    call void asm sideeffect ".space 131068", ""()
    ret i64 1

  tail:
    ret i64 0
  }

  define i64 @expand_BGTZ64(i64 %a, i64 %b) {
    %cmp = icmp eq i64 %a, %b
    br i1 %cmp, label %iftrue, label %tail

  iftrue:
    call void asm sideeffect ".space 131068", ""()
    ret i64 1

  tail:
    ret i64 0
  }

  define i64 @expand_BLEZ64(i64 %a, i64 %b) {
    %cmp = icmp eq i64 %a, %b
    br i1 %cmp, label %iftrue, label %tail

  iftrue:
    call void asm sideeffect ".space 131068", ""()
    ret i64 1

  tail:
    ret i64 0
  }

  define i64 @expand_BLTZ64(i64 %a, i64 %b) {
    %cmp = icmp eq i64 %a, %b
    br i1 %cmp, label %iftrue, label %tail

  iftrue:
    call void asm sideeffect ".space 131068", ""()
    ret i64 1

  tail:
    ret i64 0
  }

...
---

name:            expand_BEQ64
alignment:       8
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
registers:
liveins:
  - { reg: '$a0_64', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:
stack:
constants:
body:             |
  ; MIPS64-LABEL: name: expand_BEQ64
  ; MIPS64: bb.0 (%ir-block.0):
  ; MIPS64:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; MIPS64:   BNE64 $a0_64, $zero_64, %bb.2, implicit-def $at {
  ; MIPS64:     $zero = SLL $zero, 0
  ; MIPS64:   }
  ; MIPS64: bb.1 (%ir-block.0):
  ; MIPS64:   successors: %bb.3(0x80000000)
  ; MIPS64:   J %bb.3, implicit-def $at {
  ; MIPS64:     $zero = SLL $zero, 0
  ; MIPS64:   }
  ; MIPS64: bb.2.iftrue:
  ; MIPS64:   INLINEASM &".space 131068", 1
  ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; MIPS64:     $v0_64 = DADDiu $zero_64, 1
  ; MIPS64:   }
  ; MIPS64: bb.3.tail:
  ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; MIPS64:     $v0_64 = DADDiu $zero_64, 0
  ; MIPS64:   }
  ; PIC-LABEL: name: expand_BEQ64
  ; PIC: bb.0 (%ir-block.0):
  ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
  ; PIC:   BNE64 $a0_64, $zero_64, %bb.3, implicit-def $at {
  ; PIC:     $zero = SLL $zero, 0
  ; PIC:   }
  ; PIC: bb.1 (%ir-block.0):
  ; PIC:   successors: %bb.2(0x80000000)
  ; PIC:   $sp_64 = DADDiu $sp_64, -16
  ; PIC:   SD $ra_64, $sp_64, 0
  ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
  ; PIC:   $at_64 = DSLL $at_64, 16
  ; PIC:   BAL_BR %bb.2, implicit-def $ra {
  ; PIC:     $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
  ; PIC:   }
  ; PIC: bb.2 (%ir-block.0):
  ; PIC:   successors: %bb.4(0x80000000)
  ; PIC:   $at_64 = DADDu $ra_64, $at_64
  ; PIC:   $ra_64 = LD $sp_64, 0
  ; PIC:   JR64 $at_64 {
  ; PIC:     $sp_64 = DADDiu $sp_64, 16
  ; PIC:   }
  ; PIC: bb.3.iftrue:
  ; PIC:   INLINEASM &".space 131068", 1
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; PIC:     $v0_64 = DADDiu $zero_64, 1
  ; PIC:   }
  ; PIC: bb.4.tail:
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; PIC:     $v0_64 = DADDiu $zero_64, 0
  ; PIC:   }
  bb.0 (%ir-block.0):
    successors: %bb.1(0x40000000), %bb.2(0x40000000)
    liveins: $a0_64

    BEQ64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at

  bb.1.iftrue:
    INLINEASM &".space 131068", 1
    $v0_64 = DADDiu $zero_64, 1
    PseudoReturn64 undef $ra_64, implicit killed $v0_64

  bb.2.tail:
    $v0_64 = DADDiu $zero_64, 0
    PseudoReturn64 undef $ra_64, implicit killed $v0_64

...
---

name:            expand_BNE64
alignment:       8
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
registers:
liveins:
  - { reg: '$a0_64', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:
stack:
constants:
body:             |
  ; MIPS64-LABEL: name: expand_BNE64
  ; MIPS64: bb.0 (%ir-block.0):
  ; MIPS64:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; MIPS64:   BEQ64 $a0_64, $zero_64, %bb.2, implicit-def $at {
  ; MIPS64:     $zero = SLL $zero, 0
  ; MIPS64:   }
  ; MIPS64: bb.1 (%ir-block.0):
  ; MIPS64:   successors: %bb.3(0x80000000)
  ; MIPS64:   J %bb.3, implicit-def $at {
  ; MIPS64:     $zero = SLL $zero, 0
  ; MIPS64:   }
  ; MIPS64: bb.2.iftrue:
  ; MIPS64:   INLINEASM &".space 131068", 1
  ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; MIPS64:     $v0_64 = DADDiu $zero_64, 1
  ; MIPS64:   }
  ; MIPS64: bb.3.tail:
  ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; MIPS64:     $v0_64 = DADDiu $zero_64, 0
  ; MIPS64:   }
  ; PIC-LABEL: name: expand_BNE64
  ; PIC: bb.0 (%ir-block.0):
  ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
  ; PIC:   BEQ64 $a0_64, $zero_64, %bb.3, implicit-def $at {
  ; PIC:     $zero = SLL $zero, 0
  ; PIC:   }
  ; PIC: bb.1 (%ir-block.0):
  ; PIC:   successors: %bb.2(0x80000000)
  ; PIC:   $sp_64 = DADDiu $sp_64, -16
  ; PIC:   SD $ra_64, $sp_64, 0
  ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
  ; PIC:   $at_64 = DSLL $at_64, 16
  ; PIC:   BAL_BR %bb.2, implicit-def $ra {
  ; PIC:     $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
  ; PIC:   }
  ; PIC: bb.2 (%ir-block.0):
  ; PIC:   successors: %bb.4(0x80000000)
  ; PIC:   $at_64 = DADDu $ra_64, $at_64
  ; PIC:   $ra_64 = LD $sp_64, 0
  ; PIC:   JR64 $at_64 {
  ; PIC:     $sp_64 = DADDiu $sp_64, 16
  ; PIC:   }
  ; PIC: bb.3.iftrue:
  ; PIC:   INLINEASM &".space 131068", 1
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; PIC:     $v0_64 = DADDiu $zero_64, 1
  ; PIC:   }
  ; PIC: bb.4.tail:
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; PIC:     $v0_64 = DADDiu $zero_64, 0
  ; PIC:   }
  bb.0 (%ir-block.0):
    successors: %bb.1(0x40000000), %bb.2(0x40000000)
    liveins: $a0_64

    BNE64 killed renamable $a0_64, $zero_64, %bb.2, implicit-def $at

  bb.1.iftrue:
    INLINEASM &".space 131068", 1
    $v0_64 = DADDiu $zero_64, 1
    PseudoReturn64 undef $ra_64, implicit killed $v0_64

  bb.2.tail:
    $v0_64 = DADDiu $zero_64, 0
    PseudoReturn64 undef $ra_64, implicit killed $v0_64

...
---

name:            expand_BGEZ64
alignment:       8
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
registers:
liveins:
  - { reg: '$a0_64', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:
stack:
constants:
body:             |
  ; MIPS64-LABEL: name: expand_BGEZ64
  ; MIPS64: bb.0 (%ir-block.0):
  ; MIPS64:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; MIPS64:   BLTZ64 $a0_64, %bb.2, implicit-def $at {
  ; MIPS64:     $zero = SLL $zero, 0
  ; MIPS64:   }
  ; MIPS64: bb.1 (%ir-block.0):
  ; MIPS64:   successors: %bb.3(0x80000000)
  ; MIPS64:   J %bb.3, implicit-def $at {
  ; MIPS64:     $zero = SLL $zero, 0
  ; MIPS64:   }
  ; MIPS64: bb.2.iftrue:
  ; MIPS64:   INLINEASM &".space 131068", 1
  ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; MIPS64:     $v0_64 = DADDiu $zero_64, 1
  ; MIPS64:   }
  ; MIPS64: bb.3.tail:
  ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; MIPS64:     $v0_64 = DADDiu $zero_64, 0
  ; MIPS64:   }
  ; PIC-LABEL: name: expand_BGEZ64
  ; PIC: bb.0 (%ir-block.0):
  ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
  ; PIC:   BLTZ64 $a0_64, %bb.3, implicit-def $at {
  ; PIC:     $zero = SLL $zero, 0
  ; PIC:   }
  ; PIC: bb.1 (%ir-block.0):
  ; PIC:   successors: %bb.2(0x80000000)
  ; PIC:   $sp_64 = DADDiu $sp_64, -16
  ; PIC:   SD $ra_64, $sp_64, 0
  ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
  ; PIC:   $at_64 = DSLL $at_64, 16
  ; PIC:   BAL_BR %bb.2, implicit-def $ra {
  ; PIC:     $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
  ; PIC:   }
  ; PIC: bb.2 (%ir-block.0):
  ; PIC:   successors: %bb.4(0x80000000)
  ; PIC:   $at_64 = DADDu $ra_64, $at_64
  ; PIC:   $ra_64 = LD $sp_64, 0
  ; PIC:   JR64 $at_64 {
  ; PIC:     $sp_64 = DADDiu $sp_64, 16
  ; PIC:   }
  ; PIC: bb.3.iftrue:
  ; PIC:   INLINEASM &".space 131068", 1
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; PIC:     $v0_64 = DADDiu $zero_64, 1
  ; PIC:   }
  ; PIC: bb.4.tail:
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; PIC:     $v0_64 = DADDiu $zero_64, 0
  ; PIC:   }
  bb.0 (%ir-block.0):
    successors: %bb.1(0x40000000), %bb.2(0x40000000)
    liveins: $a0_64

    BGEZ64 killed renamable $a0_64, %bb.2, implicit-def $at

  bb.1.iftrue:
    INLINEASM &".space 131068", 1
    $v0_64 = DADDiu $zero_64, 1
    PseudoReturn64 undef $ra_64, implicit killed $v0_64

  bb.2.tail:
    $v0_64 = DADDiu $zero_64, 0
    PseudoReturn64 undef $ra_64, implicit killed $v0_64

...
---

name:            expand_BGTZ64
alignment:       8
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
registers:
liveins:
  - { reg: '$a0_64', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:
stack:
constants:
body:             |
  ; MIPS64-LABEL: name: expand_BGTZ64
  ; MIPS64: bb.0 (%ir-block.0):
  ; MIPS64:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; MIPS64:   BLEZ64 $a0_64, %bb.2, implicit-def $at {
  ; MIPS64:     $zero = SLL $zero, 0
  ; MIPS64:   }
  ; MIPS64: bb.1 (%ir-block.0):
  ; MIPS64:   successors: %bb.3(0x80000000)
  ; MIPS64:   J %bb.3, implicit-def $at {
  ; MIPS64:     $zero = SLL $zero, 0
  ; MIPS64:   }
  ; MIPS64: bb.2.iftrue:
  ; MIPS64:   INLINEASM &".space 131068", 1
  ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; MIPS64:     $v0_64 = DADDiu $zero_64, 1
  ; MIPS64:   }
  ; MIPS64: bb.3.tail:
  ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; MIPS64:     $v0_64 = DADDiu $zero_64, 0
  ; MIPS64:   }
  ; PIC-LABEL: name: expand_BGTZ64
  ; PIC: bb.0 (%ir-block.0):
  ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
  ; PIC:   BLEZ64 $a0_64, %bb.3, implicit-def $at {
  ; PIC:     $zero = SLL $zero, 0
  ; PIC:   }
  ; PIC: bb.1 (%ir-block.0):
  ; PIC:   successors: %bb.2(0x80000000)
  ; PIC:   $sp_64 = DADDiu $sp_64, -16
  ; PIC:   SD $ra_64, $sp_64, 0
  ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
  ; PIC:   $at_64 = DSLL $at_64, 16
  ; PIC:   BAL_BR %bb.2, implicit-def $ra {
  ; PIC:     $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
  ; PIC:   }
  ; PIC: bb.2 (%ir-block.0):
  ; PIC:   successors: %bb.4(0x80000000)
  ; PIC:   $at_64 = DADDu $ra_64, $at_64
  ; PIC:   $ra_64 = LD $sp_64, 0
  ; PIC:   JR64 $at_64 {
  ; PIC:     $sp_64 = DADDiu $sp_64, 16
  ; PIC:   }
  ; PIC: bb.3.iftrue:
  ; PIC:   INLINEASM &".space 131068", 1
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; PIC:     $v0_64 = DADDiu $zero_64, 1
  ; PIC:   }
  ; PIC: bb.4.tail:
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; PIC:     $v0_64 = DADDiu $zero_64, 0
  ; PIC:   }
  bb.0 (%ir-block.0):
    successors: %bb.1(0x40000000), %bb.2(0x40000000)
    liveins: $a0_64

    BGTZ64 killed renamable $a0_64, %bb.2, implicit-def $at

  bb.1.iftrue:
    INLINEASM &".space 131068", 1
    $v0_64 = DADDiu $zero_64, 1
    PseudoReturn64 undef $ra_64, implicit killed $v0_64

  bb.2.tail:
    $v0_64 = DADDiu $zero_64, 0
    PseudoReturn64 undef $ra_64, implicit killed $v0_64

...
---

name:            expand_BLEZ64
alignment:       8
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
registers:
liveins:
  - { reg: '$a0_64', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:
stack:
constants:
body:             |
  ; MIPS64-LABEL: name: expand_BLEZ64
  ; MIPS64: bb.0 (%ir-block.0):
  ; MIPS64:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; MIPS64:   BGTZ64 $a0_64, %bb.2, implicit-def $at {
  ; MIPS64:     $zero = SLL $zero, 0
  ; MIPS64:   }
  ; MIPS64: bb.1 (%ir-block.0):
  ; MIPS64:   successors: %bb.3(0x80000000)
  ; MIPS64:   J %bb.3, implicit-def $at {
  ; MIPS64:     $zero = SLL $zero, 0
  ; MIPS64:   }
  ; MIPS64: bb.2.iftrue:
  ; MIPS64:   INLINEASM &".space 131068", 1
  ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; MIPS64:     $v0_64 = DADDiu $zero_64, 1
  ; MIPS64:   }
  ; MIPS64: bb.3.tail:
  ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; MIPS64:     $v0_64 = DADDiu $zero_64, 0
  ; MIPS64:   }
  ; PIC-LABEL: name: expand_BLEZ64
  ; PIC: bb.0 (%ir-block.0):
  ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
  ; PIC:   BGTZ64 $a0_64, %bb.3, implicit-def $at {
  ; PIC:     $zero = SLL $zero, 0
  ; PIC:   }
  ; PIC: bb.1 (%ir-block.0):
  ; PIC:   successors: %bb.2(0x80000000)
  ; PIC:   $sp_64 = DADDiu $sp_64, -16
  ; PIC:   SD $ra_64, $sp_64, 0
  ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
  ; PIC:   $at_64 = DSLL $at_64, 16
  ; PIC:   BAL_BR %bb.2, implicit-def $ra {
  ; PIC:     $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
  ; PIC:   }
  ; PIC: bb.2 (%ir-block.0):
  ; PIC:   successors: %bb.4(0x80000000)
  ; PIC:   $at_64 = DADDu $ra_64, $at_64
  ; PIC:   $ra_64 = LD $sp_64, 0
  ; PIC:   JR64 $at_64 {
  ; PIC:     $sp_64 = DADDiu $sp_64, 16
  ; PIC:   }
  ; PIC: bb.3.iftrue:
  ; PIC:   INLINEASM &".space 131068", 1
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; PIC:     $v0_64 = DADDiu $zero_64, 1
  ; PIC:   }
  ; PIC: bb.4.tail:
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; PIC:     $v0_64 = DADDiu $zero_64, 0
  ; PIC:   }
  bb.0 (%ir-block.0):
    successors: %bb.1(0x40000000), %bb.2(0x40000000)
    liveins: $a0_64

    BLEZ64 killed renamable $a0_64, %bb.2, implicit-def $at

  bb.1.iftrue:
    INLINEASM &".space 131068", 1
    $v0_64 = DADDiu $zero_64, 1
    PseudoReturn64 undef $ra_64, implicit killed $v0_64

  bb.2.tail:
    $v0_64 = DADDiu $zero_64, 0
    PseudoReturn64 undef $ra_64, implicit killed $v0_64

...
---

name:            expand_BLTZ64
alignment:       8
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
registers:
liveins:
  - { reg: '$a0_64', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:
stack:
constants:
body:             |
  ; MIPS64-LABEL: name: expand_BLTZ64
  ; MIPS64: bb.0 (%ir-block.0):
  ; MIPS64:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; MIPS64:   BGEZ64 $a0_64, %bb.2, implicit-def $at {
  ; MIPS64:     $zero = SLL $zero, 0
  ; MIPS64:   }
  ; MIPS64: bb.1 (%ir-block.0):
  ; MIPS64:   successors: %bb.3(0x80000000)
  ; MIPS64:   J %bb.3, implicit-def $at {
  ; MIPS64:     $zero = SLL $zero, 0
  ; MIPS64:   }
  ; MIPS64: bb.2.iftrue:
  ; MIPS64:   INLINEASM &".space 131068", 1
  ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; MIPS64:     $v0_64 = DADDiu $zero_64, 1
  ; MIPS64:   }
  ; MIPS64: bb.3.tail:
  ; MIPS64:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; MIPS64:     $v0_64 = DADDiu $zero_64, 0
  ; MIPS64:   }
  ; PIC-LABEL: name: expand_BLTZ64
  ; PIC: bb.0 (%ir-block.0):
  ; PIC:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
  ; PIC:   BGEZ64 $a0_64, %bb.3, implicit-def $at {
  ; PIC:     $zero = SLL $zero, 0
  ; PIC:   }
  ; PIC: bb.1 (%ir-block.0):
  ; PIC:   successors: %bb.2(0x80000000)
  ; PIC:   $sp_64 = DADDiu $sp_64, -16
  ; PIC:   SD $ra_64, $sp_64, 0
  ; PIC:   $at_64 = LONG_BRANCH_DADDiu $zero_64, target-flags(mips-abs-hi) %bb.4, %bb.2
  ; PIC:   $at_64 = DSLL $at_64, 16
  ; PIC:   BAL_BR %bb.2, implicit-def $ra {
  ; PIC:     $at_64 = LONG_BRANCH_DADDiu $at_64, target-flags(mips-abs-lo) %bb.4, %bb.2
  ; PIC:   }
  ; PIC: bb.2 (%ir-block.0):
  ; PIC:   successors: %bb.4(0x80000000)
  ; PIC:   $at_64 = DADDu $ra_64, $at_64
  ; PIC:   $ra_64 = LD $sp_64, 0
  ; PIC:   JR64 $at_64 {
  ; PIC:     $sp_64 = DADDiu $sp_64, 16
  ; PIC:   }
  ; PIC: bb.3.iftrue:
  ; PIC:   INLINEASM &".space 131068", 1
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; PIC:     $v0_64 = DADDiu $zero_64, 1
  ; PIC:   }
  ; PIC: bb.4.tail:
  ; PIC:   PseudoReturn64 undef $ra_64, implicit killed $v0_64 {
  ; PIC:     $v0_64 = DADDiu $zero_64, 0
  ; PIC:   }
  bb.0 (%ir-block.0):
    successors: %bb.1(0x40000000), %bb.2(0x40000000)
    liveins: $a0_64

    BLTZ64 killed renamable $a0_64, %bb.2, implicit-def $at

  bb.1.iftrue:
    INLINEASM &".space 131068", 1
    $v0_64 = DADDiu $zero_64, 1
    PseudoReturn64 undef $ra_64, implicit killed $v0_64

  bb.2.tail:
    $v0_64 = DADDiu $zero_64, 0
    PseudoReturn64 undef $ra_64, implicit killed $v0_64

...
